In current manufacturing processes for FLASH memory devices, a cell channel erasing technique is becoming increasingly popular. As will be appreciated by those skilled in the art, this erasing technique involves the application of a large bias (e.g., 14-18 V) between the gates and the substrate of the cells for a period of about 100-500 ms/cycle. The same potential difference is also applied between the word lines of the FLASH memory device and the drain/source contacts.
In the meantime, the contact to gate distance, as illustratively shown in FIG. 1, becomes smaller and smaller as technology allows device sizes to shrink. For example, for 0.13 um technology this distance is below 90 nm. Thus, the quality of the dielectric and the control of the effective contact to gate distance are key points for the reliability size reduction of the FLASH cells.
Furthermore, such variables become more and more critical over the lifetime of the device. That is, if they are not accounted for during manufacturing or during device test, cell performance degradation may result in significant increases in the erasing bias. This variability can even cause the breakdown of the dielectric layer between contacts and gates, as may be seen in FIG. 2.
Presently, the contact to gate distance is monitored during manufacturing through overlay measurements between the contact mask and the word line mask at a few locations on a few wafers of each lot. Yet, there are limitations to this approach. For example, this approach provides relatively few measurement statistics, and the cost of overlay measurement is relatively high. Further, such “in line” measurements are not entirely accurate, since contact to gate distance depends also on contact and word line shape/dimension. Moreover, even if this kind of event is always localized in single defective cells, its failure rate depends largely on the intrinsic thickness of the dielectric between the contact and gate.